Graphene transistors fabricated via transfer-printing in device active-areas on large wafer

Graphene transistors fabricated via transfer-printing in device active-areas on large wafer

Xiaogan Liang, Zengli Fu, and Stephen Y. Chou

Nano Lett., 7 (12), 3840 -3844, 2007.

DOI: 10.1021/nl072566s

And now, for a pseudo-device post. As you might have read, all of the current methods in graphene synthesis have some serious shortcomings, particularly for the electronic applications (like FET) that everyone thinks graphene will work great for. This paper introduces a top-down approach to exfoliating and then patterning graphene to make a FET device.

Since I think everyone likes lists and schematics more than my paragraphs worth of text, I'll give the play-by-play and picture of the new technique, which carries the award-winning name "graphene-on-demand by cut-and-choose transfer-printing (DCT)":

a. Lithographically pattern pillars onto a stamp, very similar to a stamp for nanoimprinting (alas, the Wikipedia page doesn't have a pretty picture for it).
(aa). Coat the stamp with a nefariously defined resin.
b. Apply the stamp (with pressure) to some fancy graphite, then lift it off.
c. See if you have graphite/graphene on it.
d. Apply the stamp (with some graphene on it now) to a treated SiO2 surface, then lift it off.
e. Admire the graphene layers, produced and patterned for your amusement.


Does this sound too easy? I thought so too. They claim that the pressure exerted in step 3 actually cleaves the graphene layers and lifts off a few of them (exfoliation). They skip step C altogether, so I'm not quite sure why they include that in the diagram. Once the pillars are applied to the treated SiO2 surface then released, some of the layers stay behind (undergoing more exfoliation). The patterns they get look mostly intact, and they say that on average their films are 3-15 graphene layers thick. This is about the thickness of typical de Heer epitaxial graphene; however, we would expect the graphene layers to be stacked like graphite (since they come from graphite), instead of being blissfully and haphazardly stacked at an angle to each other (as discussed here). They don't do a lot of characterization other than SEM and AFM; how does the FET response measure up?

One of the many save-the-world properties of graphene is that it should have equal electron and hole mobilities; however, measurements made on both epitaxial and exfoliated graphene have shown significantly higher hole mobilities. Chou's graphene-on-demand shows the same trends, with a hole mobility 5 times higher than the electron mobility. In the past this has been attributed to accidental doping in preparation and handling, which seems to be a pretty big problem to me. If your mobilities are can vary 5 fold based on impurities found in the best of techniques, couldn't any change be attributed to just being better (or worse) at purifying your material?

The moral of the story is that purity is a huge huge deal when dealing with electronic applications, which anyone in the field could have told you. We can also take from this that our current methods of graphene synthesis might not give pure enough graphene to realize the amazing properties predicted by the physicists.

Oops- got a little philosophical. Back to Chou's paper: the real cool part of this paper is that they produce and pattern graphene at the same time, which could be great for industry. It's no surprise that Dr. Chou is very involved in nanoimprint lithography (NIL), since this is just NIL using graphite. Neat paper.

Disclaimer: I stole that figure from the paper, which is properly cited and can be found at the DOI link above or below.



Liang, X., Fu, Z., Chou, S. (2007). Graphene Transistors Fabricated via Transfer-Printing In Device Active-Areas on Large Wafer. Nano Letters, 7(12), 3840-3844. DOI: 10.1021/nl072566s